The present invention relates to a system and method for carrying out a non-contact burn-in test on a semiconductor wafer.
Recently, the annual production of semiconductor devices has been rocketing year after year. Generally speaking, the greater the number of devices produced per unit time, the greater the number of devices with infant mortality to be screened out therefrom by an accelerated life test called “burn-in”, for example. As is well known in the art, a burn-in test is carried out on semiconductor devices by subjecting the devices to an elevated temperature under an electrical power stress. Some of the devices that failed to withstand the stress are screened out as NO-GOs, while the other devices that could endure the stress successfully are shipped as GOs, or good products. Over the past few years, however, the time afforded to develop new semiconductor devices has been more and more limited. So the burn-in test should also be finished in a shorter amount of time. In addition, a wafer test system for use in such a burn-in test also has to have its size further reduced, since the devices under test have been downsized almost day after day.
The burn-in test has normally been carried out by applying a stress voltage onto semiconductor devices on a wafer with probe pins brought into contact with the devices under test.
FIG. 14 illustrates how the burn-in test is carried out on a semiconductor wafer 301 including a great number of semi-conductor devices thereon using a known wafer test system. As shown in FIG. 14, the wafer 301, supported on a substrate plate 302, is brought into contact with probe pins extending from a probe card 303, and then supplied with a signal delivered from a tester 304 through the pins of the card 303.
Next, it will be described how the wafer test system operates. In the example illustrated in FIG. 14, the plate 302 is grounded at a potential level of 0 V. The wafer 301 is in electrical contact with the plate 302, and each of the numerous devices on the wafer 301 also has its substrate potential fixed at 0 V. In such a state, the tester 304 outputs a signal to devices under test on the wafer 301 by way of the pins of the card 303. The devices under test, which are in contact with the pins of the card 303, start to operate in response to the signal supplied from the tester 304. As a result, a voltage is applied onto the gate electrode of each of those devices (i.e., transistors). That is to say, a voltage stress is generated between the gate electrode of the transistor and the substrate thereof. In this manner, the devices on the wafer 301 are subjected to the burn-in.
However, if test terminals provided for semiconductor devices on a wafer are of a different type from those provided for devices on another wafer, then the known wafer test system should prepare two mutually different types of probe cards for these two wafers.